The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei11-341041 filed in Nov. 30, 1999 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
1. Field of the Invention
The present invention relates to an integrated circuit loaded with phase locked loop (PLL) circuit and a lot selection system for selecting good products and bad products of the integrated circuits, and more particularly to a test circuit for testing the characteristic of the PLL circuit.
2. Description of the Related Art
Recently, in the PLL circuit, a frequency generated with respect to a reference frequency has been demanded to have a highly stable characteristic having a low jitter. For the reason, good products and bad products of the PLL circuits are selected by measuring the jitter of the frequency generated by the PLL circuit using a test circuit at a high precision.
FIG. 1 is a block diagram showing an example of the structure of a basic PLL circuit based on conventional technology.
A reference signal Fref having a reference frequency is inputted to one input terminal of a phase comparator (hereinafter referred to as PFD) 1 in this PLL circuit. The other input terminal receives a dividing signal Fvar of a frequency (Fout/N) gained by dividing an output signal Fout of a frequency oscillated by a voltage control oscillator (hereinafter referred to as VCO) 4 by N using divider (DIV). Here, the PFD1 outputs UP signal and DOWN signal depending on a differential of phase between the frequency Fout/N and the reference frequency Fref.
The UP signal and the DOWN signal outputted from the PFD 1 are inputted to a charge pump (CP) circuit 2. While the UP signal is being outputted, the CP circuit 2 outputs a high level. While the DOWN signal is being outputted, the CP circuit 2 outputs a low level.
Here, if the frequency Fout/N is lower than the Fref or is delayed in terms of phase, the PFD1 outputs the UP signal only during that delay period. Then, the CP circuit 2 to which the UP signal is inputted outputs a high level. This high level pulse is integrated by a low-pass filter (hereinafter referred to as LPF) 3 to be converted to DC level.
If the LPF3 is a passive filter comprised of resistance and capacitance, an output level of the LPF3 becomes higher than a previous state. As a result, the VCO4 oscillates at a higher frequency than a previous oscillation frequency. If this Fout/N is still lower than the Fref, the VCO4 oscillates at a higher frequency through the same process.
As a result, if the Fout/N becomes higher than the Fref, conversely, the PFD1 outputs the DOWN signal only during the same period. Then, the CP circuit 2 to which the DOWN signal is inputted outputs a low level. This low level pulse is integrated by the LPF3 to be converted to DC level. Then, the output level of the LPF3 becomes lower than its previous state. As a result, the VCO4 oscillates at a frequency lower than the previous oscillation frequency. The Fout/N and Fref are compared to each other in this way several times, so that a loop for eliminating phase error is actuated. Finally, phase differential between the Fout/N and the Fref becomes 0.Consequently, the PFD1 outputs no UP signal or DOWN signal. Then, an output of the CP circuit 2 to which no UP signal or DOWN signal is inputted becomes high impedance so that the output level of the LPF3 is maintained at the same level as the previous state. As a result, the VCO4 maintains the same frequency as the previous oscillation frequency.
The output frequency (Fout) of the PLL is determined depending on the reference frequency (Fref) and the dividing frequency (N) of the divider, so that Fout=Frefxc3x97N is established. Thus, the output frequency (Fout) is converted to a frequency gained by multiplying the reference frequency (Fref) with N.
If disturbance such as noise is applied to the PLL circuit, a generated output frequency undergoes a frequency deviation depending on power of the disturbance. The deviated output frequency returns to its original frequency by feedback control of the PLL circuit.
However, if the disturbance is generated cyclically, the generated output frequency is deviated repeatedly. If other defect than the disturbance occurs in a loop of the PLL circuit due to a problem on processing also, the generated output frequency may be deviated cyclically because the deviation of the loop response damages stability of the loop response. The amount of the deviation of the output frequency is called jitter, which is an important factor for indicating the performance of the PLL circuit.
Therefore, if an especially high precision jitter performance of a product is demanded or the jitter performance does not secure a sufficient margin with respect to its requested performance, it is necessary to measure the jitter value and determine whether the product is good or wrong. Usually when measuring the jitter value of the output frequency of the PLL or the like, a specialized, high precision measuring device such as a time interval analyzer is used.
Technical field to which the test circuit for the aforementioned PLL circuit is applied covers attached circuit of the PLL circuit used for generating a high frequency clock for internal clock of LSI such as micro computer (MCU), digital signal processor (DSP) and the like. The PLL technology uses a low frequency clock for external clock of the LSI and a high frequency clock for internal clock of the LSI, so that this is employed in applied field for improving the processing performance of the LSI, suppressing power of the entire system and the like.
Because such a specialized, high precision measuring device as a time interval analyzer is expensive and takes a long time for measurement, if this is employed for mass production of the LSI or the like, there is an increase of test cost. Further, because the PLL circuit is very likely to be affected by disturbance such as noise, measuring substrate and measuring environment need to be adjusted, thereby making it difficult to measure the jitter value of the PLL circuit at a high precision. Thus, it is difficult to measure the jitter value of the PLL loaded on the integrated circuit and select good products and bad products quickly.
The PLL circuit has a following performance as well as the jitter performance. That is, there is a fear that if the duty value of the output signal is not 50%, processing to be carried out synchronously with a period in which the duty value is less than 50% may not be executed because of shortage of time. For this reason, there has been demanded a PLL circuit in which the duty value of an output signal thereof satisfies 50% by measuring how the duty value of the output signal is deviated from 50%. However, such a measurement has not been achieved yet.
The present invention has been achieved to solve the above described problem and an object of the invention is to provide an integrated circuit which allows to determine whether it is a good or bad product by measuring the jitter value of the PLL circuit without inducing an increase of test cost and allows to measure the duty value error of the PLL circuit.
Another object of the present invention is to provide a lot selection system capable of automatically selecting whether an integrated circuit incorporating the PLL circuit is good or bad.
To achieve the above object, a first feature of they integrated circuit of the present invention includes: a phase error generation circuit for receiving a signal gained by dividing an oscillated signal from a voltage controlled oscillator and a reference signal so as to detect a phase error signal between the both; an integrating circuit for integrating error signals outputted by the phase error generation circuit; a reference voltage generation circuit for generating a predetermined reference voltage; and a voltage comparison circuit for comparing an integration result voltage outputted from the integrating circuit with a reference voltage generated by the reference voltage generation circuit.
A second feature of the integrated circuit of the present invention includes: first integrating circuit for receiving a normal turn signal of an oscillated signal from a voltage controlled oscillator and integrating it; a second integrating circuit for receiving an inverted, signal of the oscillated signal and integrating it; a subtraction circuit for obtaining a differential between integration result voltages outputted from the first and second integrating circuits.
A third feature of the integrated circuit of the present invention includes: a first integrating circuit for receiving a normal turn signal of an oscillated signal from a voltage controlled oscillator and integrating it; a second integrating circuit for receiving an inverted signal of the oscillated signal and integrating it; a subtraction circuit for obtaining a differential between integration result voltages outputted from the first and second integrating circuits; a reference voltage generation circuit for generating a reference voltage higher and a reference voltage lower than a predetermined intermediate potential; a first voltage comparison circuit for comparing a differential voltage outputted from the subtraction circuit with a higher reference voltage generated by the reference voltage generation circuit; a second voltage comparison circuit for comparing a differential voltage outputted from the subtraction circuit with a lower reference voltage generated by the reference voltage generation circuit; and a logical OR circuit for implementing logical OR of comparison results outputted from the first and second voltage comparison circuits.
Because usually, the PLL circuit carries out feedback control so as to reduce a phase error between both the reference signal and the signal gained by dividing the output signal from the voltage controlled oscillator, according to the integrated circuit of the present invention, the phase error decreases if the jitter value is small. Therefore, the integrated voltage Verr of the phase error generated by integrating the phase error signals also decreases. Conversely, if the jitter value is large, the phase error between both the reference signal and the signal Fvar gained by dividing the output signal from VCO increases. Thus, the integrated voltage Verr of the phase error generated by integrating the phase error signal also increases. For this reason, the jitter value can be evaluated easily by integrating the phase error signal in time axis direction so as to convert to the voltage value Verr and then comparing this voltage value with the reference value, although indirectly.
A first feature of the lot, selection system of the present invention includes: a phase error generation circuit for receiving a signal gained by dividing an oscillated signal from a voltage controlled oscillator and a reference signal so as to detect a phase error signal between the both; an integrating circuit for integrating error signals outputted by the phase error generation circuit; a reference voltage generation circuit for generating a predetermined reference voltage; a voltage comparison circuit for comparing an integration result voltage outputted from the integrating circuit with a reference voltage generated by the reference voltage generation circuit; a determining circuit for determining whether a LSL chip containing the respective circuits is good or wrong depending on a comparison result outputted from the voltage comparison circuit; and a lot selector for selecting the LSJ chip depending on a determination result of the determining circuit.
A second feature of the lot selection system of the present invention includes: a first integrating circuit for receiving a normal turn signal of an oscillated signal from a voltage controlled oscillator and integrating it; a second integrating circuit for receiving an inverted signal of the oscillated signal and integrating it; a subtraction circuit for obtaining a differential between integration result voltages outputted from the first and second integrating circuits; a reference voltage generation circuit for generating a reference voltage higher and a reference voltage lower than a predetermined intermediate potential; a first voltage comparison circuit for comparing a differential voltage outputted from the subtraction circuit with a higher reference voltage generated by the reference voltage generation circuit; a second voltage comparison circuit for comparing a differential voltage outputted from the subtraction circuit with a lower reference voltage generated by the reference voltage generation circuit; and a logical OR circuit for implementing logical OR of comparison results outputted from the first and second voltage comparison circuits; a determining circuit for determining whether a LSI chip containing the respective circuits is good or bad depending on a comparison result outputted from the logical OR circuit; and a lot selector for selecting the LSI chip depending on a determination result of the determining circuit.
The lot selection system of the present invention incorporates a test circuit for measuring the jitter value of the PLL circuit to indicate good product or bad product, on a LSI chip. Thus, an automatic selection system capable of selecting a good product or bad product depending on the magnitude of the jitter value can be built with a very simple structure, so that productivity of the integrated circuit and quality control thereof can be improved tremendously.
Other and further objects and features of the present invention will become obvious upon understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.